// SRAM Module
module sram #(
  parameter DATA_WIDTH = 8,
  parameter ADDR_WIDTH = 10,
  parameter DEPTH = 1024
)(
  input clk,
  input cs,
  input wen,
  input [ADDR_WIDTH-1:0] addr,
  input [DATA_WIDTH-1:0] wdata,
  output reg [DATA_WIDTH-1:0] rdata
);

  reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];

  always @(posedge clk) begin
    if (cs) begin
      if (wen) begin
        mem[addr] <= wdata;
      end
      rdata <= mem[addr]; // Read data
    end
  end

endmodule